PPC970 bus speed wierdness.

[barkmonster]

Apple would have to come up with a killer system controller because of the variable speed of FSB.

A G4 for instance has a set in stone 133, 150 or 167Mhz FSB supporting SDRAM, the L3 is 1 quarter the cpu speed with DDR SRAM.

The PPC970 has no L3 support but an FSB of 1 quarter the cpu speed with support DDR SDRAM.

Let's assume Apple are going to standardise on 400Mhz DDR II (if it comes out), these are kind of mismatched FSB and RAM speeds they'd have to deal with in whatever system controller they come up with :

1.4Ghz 350Mhz FSB x 2 with 400Mhz DDR II = FSB x 1.14 x 2 or 6.4Gb/s

1.6Ghz 400Mhz FSB x 2 with 400Mhz DDR II = FSB x 2 or 6.4Gb/s

1.8Ghz 450Mhz FSB x 2 with 400Mhz DDR II = FSB x 1.7 or 6.4Gb/s

Maybe they could even add a L3 on the system controller, a couple of Mb/s of DDR SRAM between the controller and the cpu on the models above 1.6Ghz could add a little extra performance.

I know they've had DDR 266 and 333 chipsets for the Pentium 4 for quite a while and that's either got a 100Mhz x 4 or 133Mhz x 4 FSB running on unmatched speeds of DDR RAM. It could be the same for the system controller Apple would have to use with the PPC970 except the controller would have to automatically compensate for the difference between FSB and RAM speed instead of only having to choose between either 400Mhz or 533Mhz like the Pentium 4 chipsets probably do.

Does anyone know enough about cpu/chipset design to explain how this might work ?

 

[hobie]

The FSB may be independent from the RAM bus. The G3 also has an FSB of 200mhz, but my ibook utilises 100mhz RAMs.

 

[barkmonster]

The FSB may be independent from the RAM bus. The G3 also has an FSB of 200mhz, but my ibook utilises 100mhz RAMs.

True, but that's still exactly half the FSB speed which wouldn't change with the speed of the cpu like the 970 will. It's really anyone's guess what kind of RAM or system bus speed apple would use with the 970 but ideally I'd hope it's something that can keep it fed with data. The Pentium 4 can now get 4.2Gb/s with RDRAM. The 970 would need that kind of bandwidth at least, otherwise we'd have a similar, but far more efficient situation to what we have now. A cpu that's not getting enough bandwidth to perform at it's full potential.

 

[Catfish_Man]

My guess...

Originally posted by barkmonster


True, but that's still exactly half the FSB speed which wouldn't change with the speed of the cpu like the 970 will. It's really anyone's guess what kind of RAM or system bus speed apple would use with the 970 but ideally I'd hope it's something that can keep it fed with data. The Pentium 4 can now get 4.2Gb/s with RDRAM. The 970 would need that kind of bandwidth at least, otherwise we'd have a similar, but far more efficient situation to what we have now. A cpu that's not getting enough bandwidth to perform at it's full potential.

...is that the packet based bus protocol the 970 uses (which is why it only gets 6.4GB/sec@900Mhz instead of 7.2) helps "bundle" the data in a way that makes it easy to deal with. I think the memory-northbridge bus will be a steady 800MHz x 64 bit, while the processor-northbridge bus will be variable. I'm completely guessing here, but it seems vaguely reasonable.

About that L3 on northbridge idea, that's been mentioned on arstechnica, and it seems like a really good idea. One advantage would be that whatever is in the L1/L2 cache is always in the L3 cache, so processors would only have to go to the northbridge to snoop on the other processor in dual processor setups.