Was the IIGS throttled?

[cosmichobo]

G'day,

I just came across an old video by "The 8-bit Guy" on YouTube (2015), in which he claims that the Apple IIGS's clock speed was throttled deliberately to make the Mac line up look/sell better.

Can anyone verify this statement? Was it throttled for genuine reasons (if at all), or does this stand up?

I had used Apple IIe's in primary school during the 80's, but didn't become an Apple-product-owner until 1992 with a 2nd hand Mac Classic. I became custodian over a IIGS in about 1999, but only played with it a little bit. I was very surprised how advanced it appeared to be in terms of the OS, having ADB, colour, expansion ports - though it was far too slow to consider using for anything serious at that point in time.

If the IIGS was throttled, without any physical need to do so - it just seems absurd to cripple your product?

Cheers

cosmic

 

[chabig]

Wikipedia says they were intentionally run slower than spec'ed to differentiate from the Mac.

Apple IIGS - Wikipedia

en.wikipedia.org

 

[maflynn]

Can anyone verify this statement? Was it throttled for genuine reasons (if at all), or does this stand up?

The guy knows his stuff, I've seen a number of his videos, and if says that the machines were purposely slowed down for business reasons, I'd believe him

 

[joevt]

The 65C816 could run between 1 to 14 MHz.

WDC 65C816 - Wikipedia

en.wikipedia.org

The Apple IIGS only used it at 2.8 MHz. Woz expected the IIGS to use 8 MHz?

Apple IIGS - Wikipedia

en.wikipedia.org

Besides the 2.8 MHz cap, there is actual occasions when it is necessary to throttle down to the 1.02 MHz clock of the original Apple II. Accessing the I/O area of memory would cause it to slow down so that old I/O code remained compatible. For example, disk I/O is done by the CPU so timing had to be the same.

http://mirrors.apple2.org.za/ground.icaen.uiowa.edu/MiscInfo/Empson/cpucycles

The Apple II's CPU clock was based on 14.31818 MHz for video output purposes. If you call that 14M, then bytes are read at 1M, bits are shifted at 7M for high-res graphics and 14M for low-res graphics (low-res uses four bits of a byte repeatedly 14 times for one row and the other four bits for the next row). The NTSC color burst is 3.5M. If you think of a pixel as one cycle of the color burst, then there are two bits per pixel for high-res (4 colors) and four bits per pixel for low-res (15 colors since bit patterns 1010 and 0101 are both the same grey). For high-res, only 7 bits are used per byte (they are shifted at 7M which is a multiple of the color burst 3.5M instead of at 8M) so the eighth bit is used as a half dot delay for the first 7 bits of the byte (a dot is a bit as it appears on a B&W display). This allowed for two additional possible colors in high-res mode (6 colors total). Other colors may appear between the boundary of two bytes that have different high bits (going from delayed to not delayed causes the last dot of the previous byte to be truncated - becoming a half dot, while going from not delayed to delayed causes the last dot of the previous byte to be extended by half a dot). Since a single byte is 3.5 pixels, the colors available between byte 0 and 1 will be different than the colors available between byte 1 and 2. Not all 15 colors will be possible (simplest example is grey). A dot in double high-res is equal to a dot in low-res and a half dot in high-res so you could perfectly translate low-res or high-res to double high-res (I forget if the first or last dots of a line are translatable - depends on when the cycles start in relation to the color burst for each graphics mode).

 

[mi7chy]

CPU clock speed was gradually increasing over time so not 100% convinced it was gimped but Apple could've done a much better effort especially with the later ROM03 Apple IIgs release. Apple already had a license with Zip Technologies for acceleration in the IIc+ so it wouldn't have been much effort to add it for the subsequent IIgs ROM03. That and licensing CV Tech Ramfast Rev D caching SCSI controller would've made the IIgs a screamer.

Released 1/1983 IIe 1 MHz
Released 9/1986 IIgs ROM01 2.8 MHz
Released 9/1988 IIc+ 4 MHz licensed from Zip Technologies
Released 8/1989 IIgs ROM03 2.8 MHz (should've been at least 10MHz)

Bit of trivia, the designer of Ramfast Rev D, Andrew Vogan, went on to work for Apple's storage division.

https://www.linkedin.com/in/andrew-vogan-b132004

 

[joevt]

CPU clock speed was gradually increasing over time so not 100% convinced it was gimped

The Wikipedia says Woz mentioned 8 MHz in January 1985, nearly two years before the Apple IIgs was released, so I assume that was an option at the time. The 65C816 was 2 or 3 years old then. I don't know when 14MHz became an option. I don't see anything that says it wasn't available at launch (but I haven't looked very hard).