I don’t believe we can drive these conclusions purely on what the M2 mini can do. It still would depend on how the eDP is hooked up internally. It might still be wired on the laptops in such a way that it bypasses the crossbar.
Think the argument is that the crossbar is within the M2 SoC itself.I don’t believe we can drive these conclusions purely on what the M2 mini can do. It still would depend on how the eDP is hooked up internally. It might still be wired on the laptops in such a way that it bypasses the crossbar.
I assure you it's safe to draw such conclusions based only on M2 mini capabilities. I'm just going to have to draw out a block diagram, too many people aren't familiar with how this kind of thing works inside chips.I don’t believe we can drive these conclusions purely on what the M2 mini can do. It still would depend on how the eDP is hooked up internally. It might still be wired on the laptops in such a way that it bypasses the crossbar.
Oof! I forgot what the real ratios were here and being an engineer I can't let it go.SERDES/PHY: SERializer/DESerializer. DP, USB3, and Thunderbolt (TBT) are all based on very high speed (multi-gigabit) serial links. A SERDES converts between a parallel data path at a slower clock speed and a serial data path at a much higher clock speed. For example, in PCI Express 1.0, serial line rate is 2.5 Gbps (2.5 GHz) and parallel line rate inside a chip is usually one of 156.250 MHz (16-bit datapath) or 312.500 MHz (8-bit datapath).
Nah. I love it. Thanks for your posts. I appreciate the insightsThis is probably more detail than anyone wanted.