I know that. What I meant was IPC was pretty low for Zen 4 as AMD said that >15% figure included IPC and clocks.
It is a percentage. As the base number gets higher the threshold of 10% goes higher.
2.9GHz ... 10% 0.29GHz ==> 3.19
3.9GHz ... 10% 0.39GHz ==> 4.29
4.9GHz ... 10% 0.49GHz ==> 5.39
The code being executed isn't getting more parallel. So have to artificially inject instruction level parallelism to go 'wider' once get past point have exploited most of the parallelism present. To keep the core size down AMD probably didn't go wider still so it is mostly clock. but the clock gain here is larger than previous ones in raw terms.
5950X 4.9 --> 7950X 5.5 --> 0.5GHz (Zen 3 -> Zen 4 )
3950X 4.7 --> 5950X 4.9 0.2GHz (Zen 2 -> Zen 3 )
TR2950X 4.4 --> 3950X 4.7 --> 0.3GHz (Zen 2 -> Zen 2 )
TR1950X 1950X 4.0 -> 2950X 4.4 --> 0.4GHz
Zen 2 -> Zen 3 was more of an IPC bump. Once take that, then don't necessarily get that again later relatively easily. Especially if not growing the core substantively bigger ( or hiding much bigger growth under a large fab shrink). (L2 cache grew but no mention so far if the L3 grew. Still 'stuck' with just two memory controllers . DDR5 but also bumped up the clocks. So no new 'headroom' on bandwidth there; the size of memory request queue is likely the same. )
Intel went wider with their "big" cores (Golden Cove) in Gen 12 , but also much bigger than what AMD is doing. A 6nm IO die probably costs more. The 5nm wafers are probably costing more (for now). So I doubt AMD was in the mood to just throw money at a bigger CPU core chiplet die just to win some tech porn, single threaded benchmarks.
Not new. Intel had them on their desktop CPUs for a while.
It is 'new' for the mainstream Ryzen desktop. They dumped iGPUs from the package transistor budget to chase higher core counts. So part of the issue here is that 'transistor budget' is being spent on iGPU. go from 0 to 10 is an 'infinity' percent increase. They spent 'treasure' on non CPU cores. ( Apple is probably mostly doing the same thing with M2 ).
Which was again not a huge upgrade performance wise. I still buy 6000 U series laptops in my country. I can 12th gen Intel's P and H series though both instore and online.
Not a large upgrade battery performance wise? Surely you jest. Is a laptop users absolute #1 top priority going to be maximum possible single thread performance or battery life ? In most cases it is latter ; especially if it will be used detached from a power socket for a significant amount of time per day.
I am not saying that. 90+% of the population don't need latest CPUs. In terms of going forward I believe AMD's cadence is slowing down.
Again law of large numbers in a percentages context.
Company A grows revenues $500M on a $10B revenue base 5% increase.
Company B grows revenues $100M on a $1B revenue base 10% increase.
who actually brought in more new money? The folks at Company A are snoozing all day at work?
AMD is taking turns on what they focus iterate on. Steady , methodical improvements that are not high risk. This a bigger clock leap than they taken on any of the previous iterations. After a "biggest clock" jump they'll likely switch focus on something else next. ( besides the Zen4C cores which is likely yet another dimension they are flushing out over time. )
For the Epyc package configurations these "Zen 4 " chiplets probably are a winners for the next 1-2 years. Those are far fatter margins for AMD and helps with their balance sheet. ( 6 years or so ago AMD was borrowing money to keep the lights on and spend some focused money on R&D. ). if the Bergamo/Zen4C SoC are competitive against Ampere's ARM SoCs that will help too in the higher margin space.
In the desktop space, I doubt seeing all the synergies between Ryzen 7000 and RX 7000 GPUs being laid out in the open yet. ( These (specially in the Ryzen 3/5 zone ) will certainly pair better with the RX 6500 stuff released earlier this year. ).
AMD's slide mentions some AI Acceleration which haven't been presented well so far. ( decent chance that is not a 'low' 15% increase. )
Also could be a later twist if 3D cache version 2.0 doesn't require the same level of clock hit that the first version required.
