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ffakr

macrumors 6502a
Jul 2, 2002
617
0
Chicago
Re: Ideas..

You make a few shaky assertions here.
Originally posted by Jagga
We also know that AMD holds most of the research & development rights to HyperTransport, hence their ability to incorporate memory controllers on-die and hyperinterconnects for CPU & memory controllers to run at parallel speeds to one another. (1600Mhz FSB people).
AMD is one member of the Hypertransport consortium. They don't own Hypertransport or even most of it.
Hypertransport isn't required for on die memory controllers.
I'm pretty sure the AMD FSB is not 1600 MHz. Could you post a source for this?

I hope that the new G5s in Feb PowerMacs have gone up to 2.5Ghz along with 2MB of L2 cache. Also I think that we might see a PowerBook G5 by October 2004 - my statement - because if AMD can have a system built using dual Opteron 244s with less than 6 fans @ 130nm fabrication its because they don't generate much heat because of the Hyperinterconnects.
I don't think the next 970 will have 2MB cache... it'd be too big for a small server/desktop processor (that is physically too big).
You can build an opteron or a dual G5 with 1 fan if you wanted to. the number of fans have nothing to do with heat. Granted that one fan would be big and fast and it'd have to move a lot of air.
G5 have lots of fans, but they barely turn. This has been beat to death already.
Hypertransport [hyperinterconnects??] don't produce less heat than other protocols on other AISCs running at the same clock.

Also Apple may delay the Xserve so that they can goto 4 G5s internally to better appeal to the server crowd (think Xgrids success with supercomputer PowerMacs).
The whole idea behind Grid computing is clustering computers on a loose grid. if you make super fast nodes, you decrease the need for a grid.
As with any 'cluster'.. beowolf, grid... faster nodes are better. But, you very well might be better off with 3- dual processor boxes on the grid rather than one quad proc box (or some multiple of those... 30 dual vs. 10 quads). It all depends on what you're doing.
Rest assured, I'd love to see a quad proc mac, but it'd cost a lot.
 

Telomar

macrumors 6502
Aug 31, 2002
264
44
Originally posted by jonapete2001
The athlon 64 and athlon 64 both have system bus of 1.6 ghz.
It's a 32 bit interconnect though so it requires the higher speed.
 

Genie

macrumors 6502a
May 25, 2003
604
0
heaven
Originally posted by Telomar
It's a 32 bit interconnect though so it requires the higher speed.

Wow- they only have a 32 bit bus and we have a 64?

Apple is cool!
 

legion

macrumors 6502a
Jul 31, 2003
516
0
Re: Re: Ideas..

Originally posted by ffakr

I don't think the next 970 will have 2MB cache... it'd be too big for a small server/desktop processor (that is physically too big).

Ummm... next Pentium M chip from Intel (Dothan) has a 2MB L2 cache on a 90nm process. Obviously, it's predominately meant for laptops.;)
 

ddtlm

macrumors 65816
Aug 20, 2001
1,184
0
ffakr:

I think you're desperately trying to argue that IBM isn't working on a 980 right now.
Well there's certainly no desperation involved. My position is that noone knows what IBM is working on besides "next generation PPC", which could be anything from 90nm 970's to referring to the Power5. If IBM shrinks the 970 to 90nm and uses much of the Power5 for the "980", there is no reason that they would have had to done anything 980-specific when the 130nm 970 was being developed (the original claim), or really even by now. I think everyone here is blowing IBM's development schedule way out of proportion... the 130nm Power5 not coming out till late 2004 at the earliest, I'd be very surprised if a "980" was available before that, especially at a different feature size (than the Power5). I'm still thinking a very realistic and achievable schedule would be to have 90nm PPC970's for the summer of '04, and replace them the summer of '05 or the following winter, depending on how well they scale and how well their replacement is coming along. But who knows...

ALL chip makers work on multiple generations of chips at once.
Of course they are, but derivative chips aren't being worked on separately as far ahead of time. To use your example of Sun, they probably weren't developing the US4 when the US3 was pre-release... cause they are based on the same core. The same argument could me made for the so-called 980.

IBM has said they are working on the next generation of PowerPC. Do you REALLY think that the next generation is the same chip with a die shrink?
I think that they were probably reffering to the Power5, but a 90nm 970 would technically count.

Has Apple ever called a shrunk chip a new generation? Motorola and IBM have made significant changes to past PPC chips and they haven't called them different generations of Power PC processors... just revisions.
Its all marketing driven. Just because upgraded G4's weren't hailed as revolutionary doesn't mean upgraded G5's won't be. It was certainly in Apple's favor to talk about "next generation" PPC's after the G5, regardless of what they were. They needed to speak boldly. What is "next generation" now might be treated as no big deal when they roll it out; perhaps they got their value out of calling it "next generation" and reassuring the customers.

Even if IBM chooses to simply split off a 'lite' version of the Powers instead of evolving the 9x0 line, then as they are working on several generations of Power processors (which they are), they are also making considerations for the 'lite' processors.
This is not the same thing as designing the derivitive processors.

First off, why is the A64 process so different than previous Athlons?
SOI, as you said. Should cut a lot of heat out, and the other features that add performance per clock cycle seem to help the performance/heat ratio a lot.

Now, what trap did I fall into?
You started comparing typical figures to max figures and concluded the G5 uses less power. You see, that is simply not provable with the available information. (But I'll write about the speculation a bit latter.)

I NEVER said the ~50 watts for a 970 was max. I simply stated that the link I posted indicated that the typical wattage for an Athlon was very close to the Max wattage. If typical an max were generally close on processors like the Opteron too (which is similar), then you'd expect the typical wattage of the Opteron would be nearly 80 watts.
I dunno about claims that an Athlon "typical" is similar to max, because of course typical isn't defined. Is typical idle, or running a certain application? Does IBM define it the same way? Does Moto define it the same way? Your link listing Opteron thermal power illustrates exactly what I said was true: AMD only lists one max output for the whole Opteron family. So all we know is that all current and same-family future Opterons use <= 80.6W in a worst case. As far as I know, all we know about G5's is that they "typically" generate 47W at 1.8ghz, and 18W (I think) at 1.2ghz.

You can look at "typical" vs max thermal powers for Athlons and speculate that a similar relationship exists for G5s, and then speculate that current Opterons have a max near 80W. If I make these assumptions, and also assume that a 2.0ghz G5 runs the same voltage as a 1.8ghz G5, we'd still have a 2.0ghz G5 dissipating a max of 57W. Assuming that AMD's 2.0ghz Opteron uses all 80.6W allowed by their spec, a G5 is still using about 71% the power of an Opteron. But the Opteron could easily be using less and the G5 could easily be using more. AMD's 80.6W figure applies to the whole Opteron family, and who knows how fast AMD has planned on that scaling. 80.6W might be for a 2.4ghz Opteron. Assuming that's running the same voltage as a 2.0ghz model, the 2.0ghz model is already pushed down to 67W. Note that this is not an unreasonably low figure either, an Athlon on 180nm running at 1.8ghz uses a max of 68W based on the lostcircuits link you provided. Adding SIO and going to 130nm ought to offset the 200mhz higher clock and increased transistor count without worry.

But back to my assumptions about non-increaseing voltages. Unfortuneately, its not very likely that voltage is going to remain constant for either the G5's or the Opterons. (Your lostcircuits link nicely shows Athlon voltages changeing with clockspeed.) That 10W gap could dissapear really easily, I dunno how much you know about voltage, but in case you didn't know it already, voltage is a huge deal... its why a 1.2ghz G5 uses only 38% the power of the 1.8ghz model. It would be easy to account for 10W between voltage differences from both directions. The Opteron might even end up using less power.

But hey, this is all speculation. Maybe all Opterons use 80.6W all the time (as difficult to explain as that would be), maybe the max power of a G5 is 53W at 2ghz. I don't know what the real numbers are, and I don't think you do either.

(In other news, I think I just spent too much time writing that! ;) )

Jagga:

I hope that the new G5s in Feb PowerMacs have gone up to 2.5Ghz along with 2MB of L2 cache.
Well I guess we'll never know till it happens, but since IBM went with 512k the first time around I'm betting they will remain very conservative and choose 1024k on the 90nm PPC9xx versions.

legion:

Yeah, Intel has been going a bit nutso with caches recently, haven't they? The P-M's, the P4 EE, the Itaniums... I guess they can fab it and make money though. They have nice fabs, even if some of their processors are looking poor compared to their competion. :)
 

Analog Kid

macrumors G3
Mar 4, 2003
8,933
11,532
Originally posted by Telomar
It's a 32 bit interconnect though so it requires the higher speed.

The G5 bus is 32bit as well-- two unidirectional 32 bit busses. This was done to cut the turnaround time and simplify the system controller. It doesn't do much to increase the actual bandwidth.
 

Analog Kid

macrumors G3
Mar 4, 2003
8,933
11,532
Originally posted by ddtlm
stingerman:
You are very much wrong. No FSB-based system can ever compete with an on-die memory controller of similar bandwidth, doesn't matter how fast the FSB is clocked. Signals have been travelling as fast as possible more-or-less forever, and so the limiting factor is how far the signals have to travel, and with on-die memory controllers that distance is far shorter, so the data is returned much faster. FSB systems can compete in streaming applications, where data is flowing in predictable ways, but as soon as data needs to come from random places in RAM, then all that matters is how fast it can be accessed. Increasing the clock of the RAM and the FSB will do little or nothing to address this.

For random accesses, any latency is going to be dominated by RAM access times-- where the memory controller is sitting won't make much of a difference. RAM latencies are an order of magnitude greater than the delay through a couple pipe stages with a GHz clock.

The advantages of the on-chip memory controller are power and cost. You don't need a second chip to talk to your RAM and you don't have those GHz signals driving high-capacitance board traces.

That's one of the reasons I think an onboard mem controller would help powerbook integration...

Out of curiosity-- how do dual AMD cpu systems share memory? Are they hijacking the other CPUs memory controller?
 

Genie

macrumors 6502a
May 25, 2003
604
0
heaven
Originally posted by Analog Kid
The G5 bus is 32bit as well-- two unidirectional 32 bit busses. This was done to cut the turnaround time and simplify the system controller. It doesn't do much to increase the actual bandwidth.

You mean we, just like those on the dark side, have only a measly 32 bit bus?

Or we have a 64 bit bus that's divided into two parts?
 

ffakr

macrumors 6502a
Jul 2, 2002
617
0
Chicago
Originally by ddtlm
Well there's certainly no desperation involved. My position is that noone knows what IBM is working on besides "next generation PPC", which could be anything from 90nm 970's to referring to the Power5.
The Power 5 is NOT a PowerPC. If IBM says it's working on the next generation of the PowerPC, it is NOT referring to the Power5.
If IBM shrinks the 970 to 90nm and uses much of the Power5 for the "980", there is no reason that they would have had to done anything 980-specific when the 130nm 970 was being developed (the original claim), or really even by now.
The 970 is a 'spin off' of the Power4 BUT, it is more than just a cut down version. Power4's, to the best of my knowledge, does NOT support HT links. Power4 does not support Altivec. It would be foolish of IBM to not build upon the 970 when they were working another 'lite' version of the Power5.
Peter Sandon, the chief architect of the 970 has already admitted they are looking into revising Altivec in future revisions. This is just one more clue that there are future PPCs in development.

the 130nm Power5 not coming out till late 2004 at the earliest, I'd be very surprised if a "980" was available before that, especially at a different feature size (than the Power5). I'm still thinking a very realistic and achievable schedule would be to have 90nm PPC970's for the summer of '04, and replace them the summer of '05
It's entirely possible that there will be .09 micron 970s next summer. This is really what I think also. That doesn't mean that IBM isn't working on the next generation of the PPC. And I'm not talking about a die shrunk 970, I'm talking about the next major revision of the PPC architecture.

Of course they are, but derivative chips aren't being worked on separately as far ahead of time. To use your example of Sun, they probably weren't developing the US4 when the US3 was pre-release... cause they are based on the same core.
I'm fairly certain the US 4 was being worked on when along with the US 3. The fact that one processor is based off the other doesn't prove that they can't be designed in parallel. US 4 will likely be dual core. It probably isn't feasable to make dual core US 3's on todays processes, but that doesn't mean that Sun doesn't say "this is what we are trying to accomplish for the US 3, but keep in mind that US 4 is gonna be 2 of these cores and lets work on these revisions and refinements too"

I think that they were probably reffering to the Power5, but a 90nm 970 would technically count.
Why would IBM talk up Power5 processor development when talking about Macs? Do you really, I mean honestly think that IBM reps would talk about the development of the Power5 at WWDC, or in interviews about the 970 in the Macintosh? Don't you think that when an IBM rep steps on the stage at WWDC and says 'we have a fantastic road map for you', they mean the roadmap for future PowerPCs and not the roadmap for future Power processors, which they might spin off a 'lite' hack version?

Its all marketing driven. Just because upgraded G4's weren't hailed as revolutionary doesn't mean upgraded G5's won't be.
Yes, the term 'generation' is somewhat a marketing tool, but it's also a description of a processor that is essentially new (though based off previous work). The Power5 is a new generation of Power processor over the Power4. The 604e (though it had an additional FPU and other changes) was essentially just another 604. The revisions of the G4 were just incremental revisions of the G4 architecture. They weren't what anyone would call new generations of the PowerPC processor line. What I mentioned before was, Apple, IBM, and Motorola don't have a history of calling something as trivial as a die shrink a new generation. It's never happened before and if you assume that's what they mean now, you'd have to accept that IBM and Apple are treating this processor differently than any other PowerPC processor.
SOI, as you said. Should cut a lot of heat out, and the other features that add performance per clock cycle seem to help the performance/heat ratio a lot.
But SOI, as I stated, doesn't nescessarily change the typical to max thermal ratio. I don't know if it would, I don't know if it wouldn't. I would imagine that the architecture of the processor would have more to do with this.

You started comparing typical figures to max figures and concluded the G5 uses less power.
No I didn't. I compared typical 970 wattage, to typical Athlon wattage, which was very close to max Athlon wattage. I made a direct claim that typical for the 970 is less than typical for the Athlon.
I made the assertion that it is ENTIRELY POSSIBLE that the Athlon 64 would similarly have a similar typical/max wattage since it's a bulked up Athlon. I later came back with a link to stats that indicate that Athlon64 does indeed seem to have typical wattages that are very close to Max wattage. so that point is kind of moot now isn't it.
I dunno about claims that an Athlon "typical" is similar to max, because of course typical isn't defined. Is typical idle, or running a certain application? Does IBM define it the same way? Does Moto define it the same way?
don't you think that engineers in the same industry would tend to describe microprocessors in the same basic way? There is no reason to quote chip characteristics if they aren't based on some type of standard definition. I'd have to think that Typical wattage isn't based of an idle cpu. What is so "typical" about a computer that isn't allowed to process something?
Your link listing Opteron thermal power illustrates exactly what I said was true: AMD only lists one max output for the whole Opteron family. So all we know is that all current and same-family future Opterons use <= 80.6W in a worst case. As far as I know, all we know about G5's is that they "typically" generate 47W at 1.8ghz, and 18W (I think) at 1.2ghz.
Intel also quotes large blocks of CPUs at the same wattage. This isn't uncommon. This is because the chips are the same size, on the same process, and they all run at the same core voltage and amperage. Wattage is a calculated by these features. When you calculate wattage you don't factor the frequency into the equation.
If you look a the different wattages for the 970s, they coincide with different core voltages too. The 19watt 1.2 GHz part noted in last years presentation (by Peter Sandon at MPF) was a 1.1v part while the 47watt 1.8GHz part was running 1.3v.

You can look at "typical" vs max thermal powers for Athlons and speculate that a similar relationship exists for G5s,...<snip>. But the Opteron could easily be using less and the G5 could easily be using more.
but I don't have to assume the G5s max when I've already posted Typical figures for the Opteron, which indicated that the current Opterons had Typical wattages of 80.6 watts. So, I've presented Typical wattage for the Opteron, and typical wattage for the PowerPC 970 yet you say that they could easily be more or less than the published figures??

AMD's 80.6W figure applies to the whole Opteron family, and who knows how fast AMD has planned on that scaling. 80.6W might be for a 2.4ghz Opteron.
Interesting. You really think that AMD would say, 'here are the technical details of our processors, but they aren't accurate because we are ACTUALLY giving you the wattage figures from a processor that hasn't been announced yet. I have to agree with you, that's what I'd expect AMD to do also.
Assuming that's running the same voltage as a 2.0ghz model, the 2.0ghz model is already pushed down to 67W. Note that this is not an unreasonably low figure either, an Athlon on 180nm running at 1.8ghz uses a max of 68W
First off, when I provide you with a source indicating a typical wattage of 80.6, how do you assume 67watts? Where is the leap there?
Secondly... you are comparing the wattage of a .18 micron Athlon with a .13 micron Athlong 64 which is OVER 100MILLION TRANSISTORS? The Athlong 64 is MUCH larger than an Athlong. Talk about a leap.

But back to my assumptions about non-increaseing voltages. Unfortuneately, its not very likely that voltage is going to remain constant for either the G5's or the Opterons. (Your lostcircuits link nicely shows Athlon voltages changeing with clockspeed.) That 10W gap could dissapear really easily,..<snip>... The Opteron might even end up using less power.
I'm lost again.
You are arguing with the assertion that todays 970s use less power than todays opterons and your argument now is that future Opterons and 970s will likely require higher voltages on the same process and this will make a difference some day? Huh?

But hey, this is all speculation. Maybe all Opterons use 80.6W all the time (as difficult to explain as that would be), maybe the max power of a G5 is 53W at 2ghz. I don't know what the real numbers are, and I don't think you do either.
I don't happen to design chips for IBM and AMD. That doesn't prevent us from using the data available to make reasonable assumptions. It is NOT unreasonable to assume that 970s are cooler chips than Opterons when the 970 is roughtly HALF the transistor count of the Opteron, the 970 operates at a lower core voltage, the 970 operates in roughly the same frequency range, the 970 is built on essentially the same process.

It would be extremely unlikely that the 970 would not run cooler than the Opteron given these facts (and yes those are facts and not assumptions). :)
 

ffakr

macrumors 6502a
Jul 2, 2002
617
0
Chicago
Originally posted by ddtlm

Yeah, Intel has been going a bit nutso with caches recently, haven't they? The P-M's, the P4 EE, the Itaniums... I guess they can fab it and make money though. They have nice fabs, even if some of their processors are looking poor compared to their competion. :)
Intel's cache sizes aren't hard to explain.
1) P-M is small, it's low power (cache generally doesn't add to heat as much as logic), and it's designed to run more efficiently per clock than the P4. There is a rough die size that is considered optimal for adding interconnects and for heat/density. When you make a P-M you want to say in the same optimal size window, and you can do that by adding cache. It also allows Intel to run the chip slower, at lower voltages, creating less heat, at higher computational efficiency.
2) P4 EE isn't really a P4. It is a Xeon that is being introduced as a P4 Only because the Athlon64 family is creaming the P4 in gaming benchmarks. This isn't a new chip, just an existing processor that has been rebranded.
3) Itaniums are server chips. Server chips generally have more cache because they need it. Money is also less of an issue with a server processor so designers have the luxury of using more cache. The last PA-RISC had 32 MB of cache if I recall correctly.
As for the Itanium.. it's a VLIW processor so it's designed to process multiple words at once. It also has quite a bit of bandwidth so it probably needs way more cache to keep it from getting data starved.

cheers
ffakr

(had to post seperately, last one was too big ;-) )
 

Genie

macrumors 6502a
May 25, 2003
604
0
heaven
Originally posted by Phil Of Mac
"We have already built the prototypes of next-generation PowerPC processors."

Sounds like we're talking about 980- based design?
 

manitoubalck

macrumors 6502a
Jul 17, 2003
815
0
Adelaide, Australia
I think the "Typical figures" of processor wattage is rubbish, because typical is abartary. typical for a gamer is alot higher than typical for an office worker, So in my opinion IBM and MOTO should release max wattage values.
 

ddtlm

macrumors 65816
Aug 20, 2001
1,184
0
ffakr:

Quite the discussion, I must say.

The Power 5 is NOT a PowerPC. If IBM says it's working on the next generation of the PowerPC, it is NOT referring to the Power5.
Well technically no, but since much of the Power5 will probably turn up in a Power5-lite, to me it seems reasonable for them to make the claim even if the Power5-lite was not yet its own project. (Or I still think they could have been talking about a 90nm 970).

It would be foolish of IBM to not build upon the 970 when they were working another 'lite' version of the Power5.
If IBM builds a Power5-lite from the Power4-lite and not from the Power5, then I think they've lost the economic advantage of it being a Power5-lite. But yes, if this is what they are doing then I would agree that the 980 would have been in development for some time now.

I'm fairly certain the US 4 was being worked on when along with the US 3. The fact that one processor is based off the other doesn't prove that they can't be designed in parallel. US 4 will likely be dual core.
It's a fact that the US4 will be two US3 cores with small tweaks. (Not that that's a real important point, but just to share that info.)

It probably isn't feasable to make dual core US 3's on todays processes, but that doesn't mean that Sun doesn't say "this is what we are trying to accomplish for the US 3, but keep in mind that US 4 is gonna be 2 of these cores and lets work on these revisions and refinements too"
Yeah and I'm sure IBM was thinking similarly for the Power5-lite, but I don't think that this means the lite or US4 was in development in paralell with it's parent.

The revisions of the G4 were just incremental revisions of the G4 architecture.
Well, I sort of agree, except for the jump to the 7450. That was a totally new design, but Apple chose to not mention that at all. The 7450 was probably as different from the 7410 (I think thats the number) as the Power5-lite will be from the PPC970. I'm just thinking this is all very much based on PR and marketing, and that we shouldn't read too much into "next generation" and what it means. I do think that they could have meant the Power5, or a 90nm PPC970 when they said "next generation", but maybe they didn't mean either. I don't see how we can settle that point...

I made the assertion that it is ENTIRELY POSSIBLE that the Athlon 64 would similarly have a similar typical/max wattage since it's a bulked up Athlon. I later came back with a link to stats that indicate that Athlon64 does indeed seem to have typical wattages that are very close to Max wattage. so that point is kind of moot now isn't it.
Its hardly moot, in fact the link wasn't nearly as useful as you're thinking. Just go right to AMD:

http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_8796_739^9003,00.html

Grab the "processor data sheet" and go to page 75, where its all made clear. Your link was wrong, AMD lists several thermal power figures for Opterons in general and none are labeled "typical". The "Typ" column is empty. The max thermal power for all Opterons, even those not yet released, is either 80.6W or 84.7W, depending on which figure you take. (This pick-and-choose situation obviously complicates things.)

There is no reason to quote chip characteristics if they aren't based on some type of standard definition. I'd have to think that Typical wattage isn't based of an idle cpu. What is so "typical" about a computer that isn't allowed to process something?
You cannot prove these things by trying to apply logic to the workings of large companies.

Intel also quotes large blocks of CPUs at the same wattage.
Yes in particular the P-M is listed this way, because it will throttle to make sure it stays within the limits. But this is a new phenomenon, as far as I've seen.

When you calculate wattage you don't factor the frequency into the equation.
Transistors use power when they switch, and therefore power usage is effected by clockspeed. The common formula is power usage scales the some constant times clockspeed times voltage squared. Amperage is the effect, not the cause.

Interesting. You really think that AMD would say, 'here are the technical details of our processors, but they aren't accurate because we are ACTUALLY giving you the wattage figures from a processor that hasn't been announced yet. I have to agree with you, that's what I'd expect AMD to do also.
Well actually releasing the max power for the whole family right up front makes designing cases, heatinks and motherboards that a future-compatible very easy.

First off, when I provide you with a source indicating a typical wattage of 80.6, how do you assume 67watts? Where is the leap there?
Well assuming that AMD allowed headroom for 2.4ghz and assuming voltage is constant from 2.0ghz to 2.4ghz, we can just scale the power usage by clockspeed and the 2.0ghz model would have to use about 67W.

Secondly... you are comparing the wattage of a .18 micron Athlon with a .13 micron Athlong 64 which is OVER 100MILLION TRANSISTORS? The Athlon 64 is MUCH larger than an Athlong. Talk about a leap.
Heh, I think youve made bigger leaps. ;)

You are arguing with the assertion that todays 970s use less power than todays opterons and your argument now is that future Opterons and 970s will likely require higher voltages on the same process and this will make a difference some day?
No no, I guess I didn't word things well. I'm saying that because a 2.4ghz Opteron would almost certainly use a higher voltage than a 2.0ghz model that the 2.0ghz model would be pushed down somewhere below 67W due to the effect that voltage has on power use. So the Opteron is pushing down from above, but the 2.0ghz G5 possibly (probably?) uses higher voltage than than 1.8ghz model, its gona be pushing up from below. With only 10W difference before these voltage effects, the gap could close entirely. I've made a series of assumptions to show a reasonable case in which a G5 could be using as much power or more power than an Opteron at the same clockspeed. Its based on a lot of speculation, but this is all stuff that could be true.

I don't happen to design chips for IBM and AMD. That doesn't prevent us from using the data available to make reasonable assumptions. It is NOT unreasonable to assume that 970s are cooler chips than Opterons when the 970 is roughtly HALF the transistor count of the Opteron, the 970 operates at a lower core voltage, the 970 operates in roughly the same frequency range, the 970 is built on essentially the same process.
Ah now those are some more valid points, dare I say. As far as die size and transistor count, AMD is badly effected by the larger L2 (which is not very dense, for some reason). Caches aren't big heat makers so things aren't as dire for AMD as they might at first appear. Voltage levels also do look to be in IBM's favor. So it may well be that G5's use less power than Opterons, but there is too much design-to-design variability to really nail that down. The Power4 core might be one heck of a power pig, I dunno.
 

Analog Kid

macrumors G3
Mar 4, 2003
8,933
11,532
Originally posted by ffakr
Intel's cache sizes aren't hard to explain.
1) P-M is small, it's low power (cache generally doesn't add to heat as much as logic), and it's designed to run more efficiently per clock than the P4. There is a rough die size that is considered optimal for adding interconnects and for heat/density. When you make a P-M you want to say in the same optimal size window, and you can do that by adding cache. It also allows Intel to run the chip slower, at lower voltages, creating less heat, at higher computational efficiency.

Actually, cache adds at least as much heat as logic. It also leaks like a sieve at small processes, which is why Prescott is so hot for it's clock speed even at 90nm.

It generates less heat than going to the external memory though, which is why a mobile processor might rely on larger cache.
 

Analog Kid

macrumors G3
Mar 4, 2003
8,933
11,532
Originally posted by Genie
You mean we, just like those on the dark side, have only a measly 32 bit bus?

Or we have a 64 bit bus that's divided into two parts?

It's not quite as easy as that... It's a 32bit bus because it eats data in 32bit chunks.

There's two of them-- one can only read and one can only write.

Technicallly, the CPU could read and write simultaneously meaning you're getting a little more than twice the throughput that you would with a single 32bit bus alternately reading and writing (more because it doesn't need to worry about turn around time).

In an extreme case (like a checksum, maybe) where a lot of data goes in and very little comes out, you're not getting much advantage over a standard 32bit bus.

Usually you'll be somewhere in between, I imagine.

I'm sure the folk designing this looked at the 64 signals they had for a bus and decided this was a better solution, so it must have advantages over a true 64 bit bus-- especially for a chip expected to be mostly running 32bit code.
 

Genie

macrumors 6502a
May 25, 2003
604
0
heaven
THank you- that was very helpful!

When do you think we'll be seeing a bi-directional true 64 bit buss? (double the pipe size of the current sual 32bit bus).:)
 

mvc

macrumors 6502a
Jul 11, 2003
760
0
Outer-Roa
VERBOSE

ffakr, ddtim, are you both vying for the longest post ever recorded or something?

If you keep quoting each other back and forth like this, we are going to cross some sort of info event horizon and the whole forum will implode up its own watusi.

Brevity is the soul of wit.
 

Telomar

macrumors 6502
Aug 31, 2002
264
44
First on the topic of the actual successor to the current PPC970 rather than a die shrunk version it is already in the works and has been for some time. I know that for a certainty. Expect to see some feature creep come in with the die shrink though.

Now onto the rest.

Originally posted by Analog Kid
The G5 bus is 32bit as well-- two unidirectional 32 bit busses. This was done to cut the turnaround time and simplify the system controller. It doesn't do much to increase the actual bandwidth.
If you want to be fussy then the Opteron's bus is actually dual uni-directional 16 bit buses operating at 1.6 GHz.

Originally posted by Analog Kid
For random accesses, any latency is going to be dominated by RAM access times-- where the memory controller is sitting won't make much of a difference. RAM latencies are an order of magnitude greater than the delay through a couple pipe stages with a GHz clock.

The advantages of the on-chip memory controller are power and cost. You don't need a second chip to talk to your RAM and you don't have those GHz signals driving high-capacitance board traces.

That's one of the reasons I think an onboard mem controller would help powerbook integration...

Out of curiosity-- how do dual AMD cpu systems share memory? Are they hijacking the other CPUs memory controller?
Memory latencies are significantly lower using an on-die memory controller. On-die memory controllers are also generally more efficient. For instance the memory latency out of the Athlon FX-51 is about 150 clock cycles compared to 250 for a PIV. The bandwidth is also normally as much as 10 - 15% higher despite having the same theoretical numbers.

As for lowering the cost that's certainly debatable. It does move the cost from the motherboard manufacturer to the CPU manufacturer and it does make integration little easier though.

The Opterons use a hypertransport ring that connects multiple CPUs that each connect to their RAM. It then apportions what goes to what RAM based on usages and dataset size, etc. That's done mainly by the OS though.

Originally posted by Analog Kid
Actually, cache adds at least as much heat as logic. It also leaks like a sieve at small processes, which is why Prescott is so hot for it's clock speed even at 90nm.

It generates less heat than going to the external memory though, which is why a mobile processor might rely on larger cache.
You answered why you'd want more cache in the first part of your post. Cache leaks heat badly because it's so dense. The more often you need to change what's in the cache the more switches you have. Increase cache size and you decrease switches. Better cache accessing algorithms and utilisation help somewhat too but that's more done in software.

Originally posted by Genie
When do you think we'll be seeing a bi-directional true 64 bit bus? (double the pipe size of the current sual 32bit bus).:)
The bitness of the bus is nigh on irrelevant except in terms of the bandwidth available to the bus. The POWER5 uses 2 128 bit buses but that's simply because it needs the extra bandwidth. Even dual channel DDR RAM can't feed the current bus so I wouldn't expect them to bother with the cost of 2 64 bit buses anytime soon.
 

Analog Kid

macrumors G3
Mar 4, 2003
8,933
11,532
Originally posted by Genie
THank you- that was very helpful!

When do you think we'll be seeing a bi-directional true 64 bit buss? (double the pipe size of the current sual 32bit bus).:)

I don't know that we ever will-- they may find the current structure to be more efficient. I'm sure IBM/Apple are profiling bus transactions to make sure of that.

Don't worry about bit width-- worry about throughput. Wider busses are very hard to run fast because all of the signals need to be very carefully controlled to all arrive at the same time. That's why a serial bus like FireWire (or SATA) can outpace the much wider ATA busses.

Reality check:
Who said Athlon64 had a 64bit bus at 1.6GHz? Just started going through the datasheet and I see no such thing... I see a 64bit DRAM bus going at 200MHz (presumably 400MHz data rate) and a 16bit HT bus at 1.6GHz...
 

Analog Kid

macrumors G3
Mar 4, 2003
8,933
11,532
Originally posted by Telomar
Memory latencies are significantly lower using an on-die memory controller. On-die memory controllers are also generally more efficient. For instance the memory latency out of the Athlon FX-51 is about 150 clock cycles compared to 250 for a PIV. The bandwidth is also normally as much as 10 - 15% higher despite having the same theoretical numbers.

I'm not going to say the integrated memory controller won't cut latency a little, but 100 clocks faster? Does PIV==P4? Are you accounting for the fact that the Athlon is running a 2GHz clock and P4 a 3GHz clock? I'm confused... :confused:

The ram itself has a 40ns (80 G5 core clock) latency or so on a random access. I would expect that to swamp the delays through the system controller. I could account for maybe 12-16 core clocks of additional delay, but I'm only guessing.

Where are the delays added?

10% on sustained throughput would tend to support my guess of added delay, since you have to precharge the next bank once you exceed the burst length-- essentially another random access...
 

Henriok

macrumors regular
Feb 19, 2002
226
14
Gothenburg, Sweden
ddtlm and ffakr:

Power5 is NOT a PowerPC
Actually it is, and so was Power4 and Power3 before it. They all have the full PowerPC ISA, both 32- and 64-bit instructions, in addiion to the POWER ISA and Amazon ISA (used for OS/400).

IBM constructed the 970 family with 90 nm in mind, so there won't be any trouble in the transistion to 90 nm. They have publicly stated that They'll start at 130 and move as quickly as they can to 90 nm.

There are some empty space on the 970 die that look suspicion. I figure it will be fileld with cache or is something that will be remedied in a move to 90 nm. 1 MB L2 cache is reasonable for the 970+ (using the same naming scheme as the Power-series).

IBM has been using 130 nm fab for about 2 years now, so the transistion from 130 to 90 won't be at any revolutionary pace.

It's a fact that IBM hasn't any systems using 970 themeselves yet. I think that's due to a combination could be of these reasons:
a) Apple has first dibs om 970
b) IBM wan't the 90 nm-version for heat/power issues (in blades, racks and thin clients)
c) They wan't the larget L2 cache
d) They might build a version without AltiVec.

I suspect that IBM might push the current 970 up to 2.5 GHz this winter.

The Power5-derivative is named "GR-UL" or "97x" by IBM. That's a fact. IBM hasn't publicly mentioned any "980" ever.

The 970+ is for 1H04 realease @ 2.5 GHz.
The 97x is for a '04 realease @ +2.5 GHz.

This is the same GHz rating as IBM's 1.8 GHz was, so I won't be surprised that Apple will push 970+ to 3 GHz this summer. I suspect that 97x will clock in at ~3 GHz this time next year. I havn't seen any figure of how far 95x will be pushed.

97x will inherit some cool stuff from Power5 like SMT, better power saving features and an integrated memory controller. AltiVec will be there, and it will be updated to at least 7450-standard.

I think 970+ eventually will be named 970FX, and 97x will be named 975. That'd be consistent with IBM's and Motorola's previous naming of the G3-processors. There's no reason why they should follow the naming scheme of the Power-series.

The coolest part though is that IBM will realease a 3 GHz part before Intel reaches 4 GHz. THAT's impressive. Macs going from 1 Ghz to 3 GHz in 18 months is pretty impressive.
 

ffakr

macrumors 6502a
Jul 2, 2002
617
0
Chicago
Re: VERBOSE

Originally posted by mvc
ffakr, ddtim, are you both vying for the longest post ever recorded or something?

If you keep quoting each other back and forth like this, we are going to cross some sort of info event horizon and the whole forum will implode up its own watusi.

Brevity is the soul of wit.
haha, I had to cut mine down 5x before it would actually post. that's why I responded back to back. :)
 
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