Become a MacRumors Supporter for $50/year with no ads, ability to filter front page stories, and private forums.

ffakr

macrumors 6502a
Jul 2, 2002
617
0
Chicago
Originally posted by Henriok
Actually it is, and so was Power4 and Power3 before it. They all have the full PowerPC ISA, both 32- and 64-bit instructions, in addiion to the POWER ISA and Amazon ISA (used for OS/400).

This is true, something neglected for berevity (and potentially clarity).
The Power ISA is a superset of the PowerPC ISA. Power chips can run PowerPC code, but PowerPC chips can not run Power code (well, I suppose unless it was only a subset of Power ;-)

I was really trying to say that there are two distinct product lines, though they are related (based on ISA). There is a Power line of processors.. processors designed for servers and high end workstations. There is the PowerPC line of processors, designed for low end servers, desktops, and embedded applications.
If IBM says PowerPC, they aren't talking about Power.
If IBM says Power, they aren't talking about PowerPC.

... :)
 

ffakr

macrumors 6502a
Jul 2, 2002
617
0
Chicago
Originally posted by Analog Kid
Actually, cache adds at least as much heat as logic. It also leaks like a sieve at small processes, which is why Prescott is so hot for it's clock speed even at 90nm.

It generates less heat than going to the external memory though, which is why a mobile processor might rely on larger cache.

Intel claims the high heat is a by-product of leak caused by the .09 process (thiner gates, hopping electrons...). They didn't mention the extra cache as being responsible.
I'll defer to more knowledgable people on L2 cache heat though... I'd heard it wasn't as bad as logic, but I could be missinformed.
 

yamabushi

macrumors 65816
Oct 6, 2003
1,009
1
90nm is good 65nm is wonderful

IBM should push 90nm as their standard process and lure more customers to use their fabs. They could do this and gain bragging rights by producing 65nm chips in volume by the end of 2004. Both the 970 and 980 would be good candidates as they would be naturally compared to Intel and AMD consumer level chips.
 

Henriok

macrumors regular
Feb 19, 2002
226
14
Gothenburg, Sweden
Originally posted by ffakr
The Power ISA is a superset of the PowerPC ISA. Power chips can run PowerPC code, but PowerPC chips can not run Power code.

[...]

If IBM says PowerPC, they aren't talking about Power.
If IBM says Power, they aren't talking about PowerPC.
Power1 and Power2 wasn't PowerPC-processors but the latter incarnations are. IBM actually do include Power3, Power4 and the Star-series (RS64) of processors when they are talking about PowerPC. The Power3 was even announced as "the next generation 64-bit PowerPC processor".

I wonder where the new Xbox 2-processor will fit into the extended family tree.
 

Jagga

macrumors member
Jul 14, 2003
51
0
hamilton
ffakr
I don't think the next 970 will have 2MB cache... it'd be too big for a small server/desktop processor (that is physically too big).

Why do you think 2MB will be too big for a small server/desktop, the original XServe Dual G4 had 2MB of L3 RAM per CPU. Also, in the Quicksilver models the 933Mhz G4 had 2MB, as well as the original Dual 1.0Ghz had 2MB per CPU as well?!!

the number of fans have nothing to do with heat. Granted that one fan would be big and fast and it'd have to move a lot of air.

I mentioned the fan issue in regards to overall system cooling - the entire box - as AMD is trying to move more data per second than IBM 970 for their A64-fx-51. Moving data at high speeds will cause heat, the faster the more at current copper technology (evidence the need for SOI cpu). Again sorry for the heat issue bore but I meant it related to Laptops, not desktops as the A64 will supercede the G5 in laptops.


The whole idea behind Grid computing is clustering computers on a loose grid. if you make super fast nodes, you decrease the need for a grid.

this I understand but their are motherboard manufacturers for AMD that have four CPU on one board. With almost no/low latency between cpu's and memory. DOn't get me wrong I love Apple and don't plan on purchasing intel/amd for the forseeable future, yet I do think that IBM & hence Apple got shifted in the design and usuage of hyperconnects that use hypertransport in the 970. Just think a 40U server rack with 40 XServes, each with 4 G5s that can communicate highly efficiently at super speeds between one another, and between each others memory banks. That would be better than say 2 G5s per Xserve's in the same situation, especially when connecting all of them in a cluster.

Genie


Wow- they only have a 32 bit bus and we have a 64?
along with
Originally posted by Telomar It's a 32 bit interconnect though so it requires the higher speed.

Actually the interconnects are 64-bit and data travels in both directions at that 64bit rate, in the A64 while the Opteron is 32-bit."Yes,
128-bit data path @ CPU core frequency"
this coming from jonapete2001 AMD site link.

ffakr

But SOI, as I stated, doesn't nescessarily change the typical to max thermal ratio. I don't know if it would, I don't know if it wouldn't. I would imagine that the architecture of the processor would have more to do with this.

Isn't the process, imbedding copper into Silcone to stretch the copper then fold-shrink it, actually part of the architecture of the processor?? Why else do it other than make electrons travel faster?! If that alone then the G5 should be at say 3Ghz already, but shrinking the die size does this, but architecture is how the build it, hence SOI right?!


It is NOT unreasonable to assume that 970s are cooler chips than Opterons when the 970 is roughtly HALF the transistor count of the Opteron, the 970 operates at a lower core voltage, the 970 operates in roughly the same frequency range, the 970 is built on essentially the same process.

understand the facts but "essentially" doesn't mean exactly. IBM had already started producing working, not test yields of the G5 for Apple when AMD approached them with their problem of fabricating the A64 and recently new Opterons. AMD uses more HyperTransport interconnects in the chip than the G5 and it incorperates the memory controller. This caused their problem, yet IBM was able to solve it for them; somehow imbedding the copper in SOI shrinking the copper/SOI combo then removing the SOI to fold or whatever to the copper before coating SOI back onto it. Yes I sound like I've been heating shovel dirt but I DID read it somewhere on net, just cannot remember where. Might have been one of the first reviews of the A64 by wintel fan sites. However, this may change what the max operating heat.

ddtlm

Transistors use power when they switch, and therefore power usage is effected by clockspeed.

I may know not as much as you do but on this paraphrase qoute, hasn't generations of the G4 in powerbooks and now the iBook used less power with increasing clockspeeds??

Telomar

The bitness of the bus is nigh on irrelevant except in terms of the bandwidth available to the bus. The POWER5 uses 2 128 bit buses but that's simply because it needs the extra bandwidth. Even dual channel DDR RAM can't feed the current bus so I wouldn't expect them to bother with the cost of 2 64 bit buses anytime soon.

Um bitness of the bus is relevant, especially in terms of using PCI-X and AGP8x along with memory, DVD-R and SATA drives all jockeying for the maximum bits/bytes to transfer data to and from the CPU, DDRmemory and each other!! Why else do you think the Power5, G5, G4, P4, A64/Opteron need the extra bandwidth compared to say a P2 or G3?!?!:D

Guess I'm just being cheeky
 

legion

macrumors 6502a
Jul 31, 2003
516
0
Just for clarification in nomenclature:

IBM's chips for servers/workstations are POWER (all caps) series. It is an acronymn (allbeit, a clever one) and describes the chip architecture: Performance Optimized with Enhanced RISC (POWER)

The chips Apple use are PowerPC (no caps) and is a trademark of IBM's.

For more on the PowerPC see:
http://www-1.ibm.com/servers/eserver/pseries/hardware/whitepapers/power/ppc_arch.html#intro
which is a very comprehensive paper for laymen on the PowerPC architecture and its development.
 

ffakr

macrumors 6502a
Jul 2, 2002
617
0
Chicago
Originally posted by Phil Of Mac
PowerPC is a variant of the POWER system architecture for personal computing applications.
According to an old book on the PowerPC (forgot name, black with red name.. tossed it years ago), The PPC is based off POWER but it's based off POWER back when POWER was a 6 chip set not one cpu! That is, 6 component processors made up the POWER CPU.
Old stuff (we actually had an OLD POWER in a lab at my last place.. freaked out my techs when they looked inside)

anywho.. Apparently the PowerPC also took design queues from some Motorola RISC design, though I can't possibly remember which one at this point. I don't think it was very successful.

Just saying. :)
 

daveL

macrumors 68020
Jun 18, 2003
2,425
0
Montana
Originally posted by ffakr
anywho.. Apparently the PowerPC also took design queues from some Motorola RISC design, though I can't possibly remember which one at this point. I don't think it was very successful.

Just saying. :)

Moto 88K. Used in the DG Aviion line of Unix machines (SysVr4). Early 90s. Too little, too late. Seems to be Moto's corporate anthem. Some things don't change, much.
 

ffakr

macrumors 6502a
Jul 2, 2002
617
0
Chicago
Originally posted by Jagga

Why do you think 2MB will be too big for a small server/desktop, the original XServe Dual G4 had 2MB of L3 RAM per CPU. Also, in the Quicksilver models the 933Mhz G4 had 2MB, as well as the original Dual 1.0Ghz had 2MB per CPU as well?!!
That was L3 Cache chips in addition to the CPU. I'm talking about adding an additional 1.5 MB of L2 on the same die as the CPU.
IBM could easily make a PowerPC with 2MB of L2 cache, even on .13 micron, but it would be a lot bigger physically. It would take up more space on an expensive multilayer platter. This would drive down the number of chips per wafer and increase the cost of each processor. It would also increase the heat dissipation of the processor.
IBM will take multiple criteria into consideration when upping the cache:
- what is an optimal CPU die size (mm^2) to work with, dies too small are difficult to work with.. difficult to connect to the packaging.
- what amount of L2 is reasonable for typical desktop use at a given processor speed (with a fast system bus)
- at what point do increasing L2 sizes get outweighed by increasing cost
...

Isn't the process, imbedding copper into Silcone to stretch the copper then fold-shrink it, actually part of the architecture of the processor?? Why else do it other than make electrons travel faster?! If that alone then the G5 should be at say 3Ghz already, but shrinking the die size does this, but architecture is how the build it, hence SOI right?!
Well, the Copper is way too small to fold and shrink it. CPUs aren't made like horseshoes or swords. The metal is formed by etching it with light. (pretty cool). CPUs manufacturing is closer to silkscreening tshirts than it is to hammering out a metal frame.
As far as "Architecture", I don't know of anyone who would describe a computer CPU architecture by including the process it's produced on. The process would be important in determining what Architecture would be feasible, but when I say architecture I'm basically refering to the layout of the processor logic, not the silicon.

I may know not as much as you do but on this paraphrase qoute, hasn't generations of the G4 in powerbooks and now the iBook used less power with increasing clockspeeds??
Not the same thing. The architecture evolved, and the transistor count of the G4 family has increased, but this has happened as the process has evolved and shrunk, and (yes) as the architecture has evolved. Motorola designs the G4 to be a low power embedded processor just as much (if not more) than it designs it to be a desktop processor.
OTOH, if you hold everything else consistent, process size, process materials... and you make the CPU bigger, or if you raise the core voltage to push the clock speed up, you'll generate more heat not less.


Um bitness of the bus is relevant, especially in terms of using PCI-X and AGP8x along with memory, DVD-R and SATA drives all jockeying for the maximum bits/bytes to transfer data to and from the CPU, DDRmemory and each other!! Why else do you think the Power5, G5, G4, P4, A64/Opteron need the extra bandwidth compared to say a P2 or G3?!?!:D
I think you missed the point here. I think the original argument was NOT that bitness was irrelevent, rather that you can't rely on the bit width. It's ALL ABOUT BANDWIDTH. You can have a 1 bit wide serial bus running super fast that has more bandwidth than a 64bit wide bus that runs much slower. This is why Serial ATA is faster than older parallel ATA.
It doesn't really matter if one processor has 32bit wide system pipes, or 128 bit wide pipes... what it comes down to is how much data can be pushed through those pipes.
So... Bitness isn't directly relevent to all those peripherals and buses you mentioned... the available bandwidth is. This why 16bit HT pipes are more than fast enough for all the external buses on a modern machine (usb, firewire, SATA...)
Also, I thought I'd mention that alot of the stuff you mentioned doesn't need lots of bandwidth to the CPU. DMA is direct memory access and it used on all modern peripherals. Not only that, AGP is designed to allow video cards to have direct access to the system memory if needed. just picking nits.
 

sethypoo

macrumors 68000
Oct 8, 2003
1,583
5
Sacramento, CA, USA
This is so cool!

Can't wait until they solve all the heating problems and get a 2 or 3Ghz G5 into a 12" PowerBook. Some Firewire 800 ports and a standard DV out would be great too!

:) :rolleyes: :D
 

Henriok

macrumors regular
Feb 19, 2002
226
14
Gothenburg, Sweden
I made this PDF_to illustrate the family tree of the POWER, PowerPC and PowerPC-AS (Amazon) processors. I have not included the majority of embedded processors but that's something I want to do in the future.

The chart is as complete as I can make it. If anyone have any additional information or suggestions. Feel free to email me, so I can correct or update it.

I thought it might be of interesst to the crowd here. Please note that the specs, names and release dates of future processors are moving targets.
 

Genie

macrumors 6502a
May 25, 2003
604
0
heaven
Originally posted by Henriok
I made this PDF_to illustrate the family tree of the POWER, PowerPC and PowerPC-AS (Amazon) processors. I have not included the majority of embedded processors but that's something I want to do in the future.

The chart is as complete as I can make it. If anyone have any additional information or suggestions. Feel free to email me, so I can correct or update it.

I thought it might be of interesst to the crowd here. Please note that the specs, names and release dates of future processors are moving targets.

That is a very detailed chart- must have taken you days!
 

daveL

macrumors 68020
Jun 18, 2003
2,425
0
Montana
Originally posted by Henriok
I made this PDF_to illustrate the family tree of the POWER, PowerPC and PowerPC-AS (Amazon) processors. I have not included the majority of embedded processors but that's something I want to do in the future.

The chart is as complete as I can make it. If anyone have any additional information or suggestions. Feel free to email me, so I can correct or update it.

I thought it might be of interesst to the crowd here. Please note that the specs, names and release dates of future processors are moving targets.
Very nice work! One thing I noticed: You have no 97x counterpart to the Power5+, leaving a rather long stretch without an obvious 97x improvements. I'm not saying there needs to be an association (97x -> Power5+), only that you don't indicate one.

Thanks! And please post updates!
 

Henriok

macrumors regular
Feb 19, 2002
226
14
Gothenburg, Sweden
Originally posted by daveL
Very nice work! One thing I noticed: You have no 97x counterpart to the Power5+, leaving a rather long stretch without an obvious 97x improvements. I'm not saying there needs to be an association (97x -> Power5+), only that you don't indicate one.
First.. it did take days, several days. This is the 7:th version of it too. Each revision adds processors (this one added the Xbox 2-processor and my best guess is that it will be based on the 970) and revised graphics.

The only processors that goes into the chart are processors that either have a confirmed existence, or are rumoured to come. I also must have some sort of technical spefification too, like what fab it'll be manufactured in, or what frequency it'll run in and so forth. I haven't seen any rumor of a successor to 97x, but I'm certain that there will be one. I just don't have any data on it, so it won't be on my chart 'til there is.

And.. if there is one, I bet it'll be based on 97x, not Power5+. Just like 970+ is based on 970, not Power4+. The plus-processors are quite similar to their predecessor, but made on a smaller fab.
 

Rincewind42

macrumors 6502a
Mar 3, 2003
620
0
Orlando, FL
Originally posted by yamabushi
So would that make a 65nm 970 a 970++?:)

I doubt we will ever see the 970 on a 65nm process if it goes to a 90nm process. The 97x will probably start at 90nm and goto 65nm before that could happen.
 

yamabushi

macrumors 65816
Oct 6, 2003
1,009
1
Unit cost could be a driving force to move the process down. Adding transistors to modify the current design would be counterproductive to cost control. A slightly improved 970 at 65nm and low clock speeds could serve as a complete replacement of the G4. I believe the G4 has a poor price to performance ratio at release dates compared to other PPC chips. I think that a low clock 65nm 970 would be superior in this regard, especially so on larger wafers. Higher clock speed versions of the same chip could make their way into midrange systems and replace 90nm chips. The next large evolutionary step (980) could start on this process for high end systems. This all would only hold true if full scale production on the 65nm process could be realized within one year, which is possible.
 

Henriok

macrumors regular
Feb 19, 2002
226
14
Gothenburg, Sweden
The PDF is updated. The major thing that's new is fabrication processes. From 1.2 microns (1992) to 45 nanometer (2008). I haven't been able to get data om the early processors (like POWER1) so that's a white spot on my map unfortunately.

Yeah I know that the chart is quite messy now, but it's not completely unreadable :)

Some other subtle corrections and additions went into this version too.

Enjoy!
 

yamabushi

macrumors 65816
Oct 6, 2003
1,009
1
It's interesting that IBM chose their current low end 970 at 1.6GHz for the current blade server. If we were to make the assumption that they will use chips with similar thermal properties for the next blade server, that would place the 90nm 970 at 2.4GHz close to the 130nm 970 at 1.6GHz. This is great news because it could mean that a 90nm 970 at 2.8GHz might be feasible at some point in 2004.
 
Register on MacRumors! This sidebar will go away, and you'll see fewer ads.